The present invention relates to error checking and more particularly to determining whether more than one line is up.
A common problem in computers is to select one out of n lines for a transmission of a signal thereon. The selection process usually compares a signal indicating each of the lines to an incoming signal and if the system is operating properly a match will occur on one and only one of the lines. However, at times errors will occur and more than one line will be selected. When this happens data will be misdirected and errors will occur.
A typical situation is the transmission of data to a memory. The outputs of the n lines are passed through an encoder to generate a signal of n bits where n = 2.sup.m. If two lines are up of course the encoder is going to give an erroneous signal on the m lines to the decoder of the memory and data will either be placed in or removed from the wrong position in the memory. A number of schemes have been generated to determine whether more than one line is up. Most of these schemes require significant amounts of apparatus to implement and therefore it is desirable to produce a scheme that will check the propriety of the output signal of the encoder with a minimum of circuitry.